Test MP+dmb.sy+pos-[fr-rf]-addr-pos-addr

AArch64 MP+dmb.sy+pos-[fr-rf]-addr-pos-addr
"DMB.SYdWW Rfe PosRR FrLeave RfBack DpAddrdR PosRR DpAddrdR Fre"
Cycle=Rfe PosRR FrLeave RfBack DpAddrdR PosRR DpAddrdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR FrLeave RfBack DpAddrdR PosRR DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X6=z; 1:X10=x;
2:X1=y;
}
 P0          | P1                   | P2          ;
 MOV W0,#1   | LDR W0,[X1]          | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]          | STR W0,[X1] ;
 DMB SY      | LDR W3,[X1]          |             ;
 MOV W2,#1   | EOR W4,W3,W3         |             ;
 STR W2,[X3] | LDR W5,[X6,W4,SXTW]  |             ;
             | LDR W7,[X6]          |             ;
             | EOR W8,W7,W7         |             ;
             | LDR W9,[X10,W8,SXTW] |             ;
Observed
    y=2; x=1; 1:X9=0; 1:X3=2; 1:X2=1; 1:X0=0;